The present invention relates to field effect transistors, and more particularly to a compound semiconductor field effect transistor.
Various proposals have been made for improving the performance of field effect transistors.
In GaAs MESFET one type of compound semiconductor field effect transistor known as a structure such as shown in FIG. 1 has been proposed in order to achieve improved performance (Journal of Technical Disclosure Vol. 6-16, No. 81-4352).
The structure comprises a semi-insulating GaAs substrate 1, an active n-type layer 2, and a buried p-type layer 3 provided between the, substrate 1 and the layer 2.
The main role of the buried p-type layer 3 is to suppress short channel effect. The short channel effect is the phenomenon that as the gate length L is decreased the threshold voltage is significantly shifted to the negative direction. In other words, the short channel effect is the phenomenon produced in that electrons injected from a source n.sup.+ -type layer 5 to the semi-insulating GaAs substrate 1 flow into a drain n.sup.+ -type layer 6. In other words, in addition to the normal current path flowing through the active n-type layer 2 there is another current path flowing through the semi-insulating GaAs substrate 1. Consequently, the buried p-type layer 3 is provided so that a barrier at the side of the substrate is made high. In this constitution, injection of electrons to the substrate 1 is suppressed and the above-mentioned other current path is eliminated so as to suppress the short channel effect.
The buried p-type layer 3 in this structure is of low concentration and totally depleted, so that parasitic capacitance between the active n-type layer 2 and the buried p-type layer 3 or between the n.sup.+ -type layers 5, 6 and the buried p-type layer 3 is reduced and the device can act at high speed. Numeral 7 designates a gate electrode, numeral 8 a source electrode, and numeral 9 a drain electrode. A similar device is disclosed also in Japanese patent application laid-open No. 211783/1982.
However, the inventor has found that the GaAs MESFET with above-mentioned structure is susceptible to .alpha.-particle. That is, a memory such as an SRAM (Static Random Access Memory) constituted using this device is subjected to destruction of the stored information every time the .alpha.-particles strikes the memory. This phenomenon is called soft error.
Soft error in Si devices was found by T. C. May and M. H. Woods in 1979 (T. C. May and M. H. Woods, IEEE Trans, Electron Device, ED-26, p2, 1979).
The generating mechanism of the soft error in the Si device is usually thought to be as follows. The stored information is held as existence of charge stored in a capacitor of a memory cell in the case of a DRAM (Dynamic Random Access Memory) and as the height of potential at a node in a memory cell in the case of an SRAM. When one .alpha.-particle enters into the Si substrate, pairs of electrons and holes of 10.sup.6 in number are generated along the .alpha.-particle track in the Si substrate, and the electrons or the holes are diffused or drift in the substrate and flow into the capacitor or the node. Therefore the charge amount stored in the capacitor or the potential of the node varies significantly and the memorized information held therein is destroyed. Also in the SRAM constituted using the GaAs MESFET having the buried p-type layer as shown in FIG. 1, the soft error seems to be generated by a similar mechanism.
Next, difference in the soft error phenomenon between the Si device and the GaAs MESFET having the structure of FIG. 1 will be described.
In the Si device, if the carriers generated along the track of one .alpha.-particle are 10.sup.6 in the total number, the total amount of the charge flowing in the capacitor or the node is 160 fC at most (corresponding to flowing-in of all generated carriers) and not beyond 160 fC.
The inventor has repeated the measurements in the operation state of the GaAs MESFET having the structure of FIG. 1, and has found the difference between the GaAs MESFET and the Si device as follows.
In the GaAs MESFET having the structure of FIG. 1, the charge amount flowing in the capacitor or the node becomes several times larger than in the Si device when one .alpha.-particle enters the substrate.
This phenomenon means that the GaAs MESFET having the structure of FIG. 1 is more liable to the soft error caused by the .alpha.-particles than comparison to the conventional Si device.
This phenomenon means also that a carrier multiplication mechanism which multiples the charge flowing in the node exists in the GaAs MESFET having the structure of FIG. 1.
As one of the carrier multiplication mechanisms, the inventor has found the existence of following mechanism. In this mechanism, the total amount of any of the positive charge (due to a hole) and the negative charge (due to an electron) is an equal quantity of 160 fC. Since the buried p-type layer 3 of the conventional structure is totally depleted, when voltage is applied to the drain n.sup.+ -type layer 6, electric line of force extend from the drain n.sup.+ -type layer 6 to the source n.sup.+ layer 5. Thus, drifting of the generated carriers is promoted by the electric lines of force. Mobility of electron to determine the drift speed of carriers in GaAs is ten times or more larger than that of holes. Consequently, after electrons are completely absorbed to the drain n.sup.+ -type layer 6, positive holes still remain in the substrate. Thus, the potential barrier at the side of the substrate is lowered, and injection of electrons from the source n.sup.+ -type layer 5 is promoted. Thus, a thereby subsidiary current path is formed and new current flows to the drain side. This mechanism is similar to the mechanism of the short channel effect. Since the flowing-in charge becomes several times as large as 160 fC, carrier multiplication is observed.
In the above description, since conduction type of the active layer 2, the source region 5 and the drain region 6 in FIG. 1 is made n-type and conduction type of the buried layer 3 is made p-type, holes generated by .alpha.-particles remain in the substrate and the carrier multiplication occurs. On the contrary, if conduction type of the active layer 2, the source region 5 and the drain region 6 in FIG. 1 is made p-type and conduction type of the buried layer 3 is made n-type, the multiplication effect of carriers does not occur, because the holes generated by .alpha.-particles remain in the substrate so as to suppress injection of holes from the source side. In this case, however, if one .alpha.-particle enters into the device, the total amount of charge flowing in the electrode becomes about 140 fc at maximum value and is still too large to avoid the soft error.
As above described, in the structure of providing the totally depleted buried layer under the active layer in order to prevent the short channel effect, the soft error due to .alpha.-particle cannot be completely prevented. Accordingly, a field effect transistor with structure to prevent both short channel effect and the soft error due to .alpha.-particle has been desired.